module tb;

	// Inputs
	reg clk;
	reg rst;
	reg reference_signal;

	// Outputs
	wire controlled_signal;
	wire [15:0] count_cnt;

	// Instantiate the Unit Under Test (UUT)
	DPLL u0_DPLL(
		.clk(clk), 
		.rst(rst), 
		.reference_signal(reference_signal), 
		.controlled_signal(controlled_signal), 
		.count_cnt(count_cnt)
	);
	
always #1 clk=~clk;
always #51000 reference_signal=~reference_signal;

initial begin
  clk=0;
	reference_signal=0;
	rst=0;
	
	#120
	rst=1;

  #1000000 $finish;
end
      
initial begin            
  $dumpfile("wave.vcd"); //生成的vcd文件名称
  $dumpvars(0, tb);      //tb模块名称
end

endmodule
